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72 Mb (2M x 36 & 4M x 18) DDR-IIP (Burst of 2) CIO Synchronous SRAMs
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(2.5 Cycle Read Latency)
Advanced Information May 2009
* Two echo clocks (CQ and CQ) that are delivered simultaneously with data. * +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF. * HSTL input and output levels. * Registered addresses, write and read controls, byte writes, data in, and data outputs. * Full data coherency. * Boundary scan using limited set of JTAG 1149.1 functions. * Byte write capability. * Fine ball grid array (FBGA) package - 15mm x 17mm body size - 1mm pitch - 165-ball (11 x 15) array * Programmable impedance output drivers via 5x user-supplied precision resistor.
Features
* 2M x 36 or 4M x 18. * On-chip delay-locked loop (DLL) for wide data valid window. * Common data input/output bus. * Synchronous pipeline read with self-timed late write operation. * Double data rate (DDR-IIP) interface for read and write input ports. * Fixed 2-bit burst for read and write operations. * Clock stop support. * Two input clocks (K and K) for address and control registering at rising edges only. * Industrial temperature available upon request.
Description
The 72Mb IS61DDPB22M36 and IS61DDPB24M18 are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have a common I/O bus. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the Timing Reference Diagram for Truth Table on page 8 for a description of the basic operations of these DDR-IIP (Burst of 2) CIO SRAMs. The input addresses are registered on all rising edges of the K clock. The DQ bus operates at double data rate for reads and writes. The following are registered internally on the rising edge of the K clock: * Read and write addresses * Address load * Read/write enable Byte writes * Data-in * Data-out The following are registered on the rising edge of the K clock: * Byte writes * Data-in for second burst addresses * Data-out Byte writes can change with the corresponding datain to enable or disable writes on a per-byte basis. An internal write buffer enables the data-ins to be registered one cycle later than the write address. The first data-in burst is clocked with the rising edge of the next K clock, and the second burst is timed to the following rising edge of the K clock. During the burst read operation, at the first burst the data-outs are updated from output registers off the second rising edge of the K clock (2.5 cycles later). At the second burst, the data-outs are updated with the fourth rising edge of the corresponding K clock (see page 8). The device is operated with a single +1.8V power supply and is compatible with HSTL I/O interfaces.
Integrated Silicon Solution, Inc.
Rev. 00A 03/31/08
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72 D Mb (2M x 36 & 4M x 18) DDR-IIP (Burst of 2) CIO Synchronous SRAMs
x36 FBGA Pinout (Top View)
1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC Doff NC NC NC NC NC NC TDO 2 NC/SA* DQ27 NC DQ29 NC DQ30 DQ31 VREF NC NC DQ33 NC DQ35 NC TCK 3 SA DQ18 DQ28 DQ19 DQ20 DQ21 DQ22 VDDQ DQ32 DQ23 DQ24 DQ34 DQ25 DQ26 SA 4 R/W SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 5 BW2 BW3 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 6 K K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS SA NC NC 7 BW1 BW0 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 LD SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA 10 SA NC
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11 CQ DQ8 DQ7 DQ16 DQ6 DQ5 DQ14 ZQ DQ4 DQ3 DQ2 DQ1 DQ10 DQ0 TDI
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DQ17 NC DQ15 NC NC VREF DQ13 DQ12 NC DQ11 NC DQ9 TMS
* The following pins are reserved for higher densities: 2A for 144Mb
*
BW0 controls writes to DQ0-DQ8; BW1 controls writes to DQ9-DQ17; BW2 controls writes to DQ18-DQ26; BW3 controls writes to DQ27-DQ35.
x18 FBGA Pinout (Top View)
1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC Doff NC NC NC NC NC NC TDO * 2 SA DQ9 NC NC NC DQ12 NC VREF NC NC DQ15 NC NC NC TCK 3 SA NC NC DQ10 DQ11 NC DQ13 VDDQ NC DQ14 NC NC DQ16 DQ17 SA 4 R/W SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 5 BW1 NC/SA* SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 6 K K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS SA NC NC 7 NC/SA* BW0 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 LD SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA 10 SA NC DQ7 NC NC NC NC VREF DQ4 NC NC DQ1 NC NC TMS 11 CQ DQ8 NC NC DQ6 DQ5 NC ZQ NC DQ3 DQ2 NC NC DQ0 TDI
The following pin is reserved for higher densities: 7A for 144Mb, 5B for 288Mb.
* BW0 controls writes to DQ0-DQ8; BW1 controls writes to DQ9-DQ17
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Pin Description
Symbol K, K CQ, CQ Doff SA SA DQ0-DQ8 DQ9-DQ17 DQ18-DQ26 DQ27-DQ35 DQ0-DQ8 DQ9-DQ17 R/W LD 6B, 6A 11A, 1A 1H Pin Number Input clock. Output echo clock. DLL disable when low. Description
3A, 9A, 10A, 4B, 8B, 5C, 7C, 5N, 6N, 7N, 4P, 5P, 7P, 8P, 3R, 4R, 2M x 36 address inputs. 5R, 7R,8R, 9R 2A, 3A, 9A, 10A, 4B, 8B, 5C, 7C, 5N, 6N, 7N, 4P, 5P, 7P, 8P, 3R, 4M x 18 address inputs. 4R, 5R, 7R, 8R, 9R 11P, 11M, 11L, 11K, 11J, 11F, 11E, 11C, 11B 10P, 11N, 10M, 10K, 10J, 11G, 10E, 11D, 10C 3B, 3D, 3E, 3F, 3G, 3K, 3L, 3N, 3P 2B, 3C, 2D, 2F, 2G, 3J, 2L, 3M, 2N 11P, 10M, 11L, 11K, 10J, 11F, 11E, 10C, 11B 2B, 3D, 3E, 2F, 3G, 3K, 2L, 3N, 3P 4A 8A
2M x 36 DQ pins
4M x 18 DQ pins Read/write control. Read when active high. Synchronizes load. Loads new address when low. 2M x 36 byte write control, active low. 4M x 18 byte write control, active low. Input reference level. Power supply. Output power supply. Ground Output driver impedance control. IEEE 1149.1 test inputs (1.8V LVTTL levels). IEEE 1149.1 test output (1.8V LVTTL level). x36 Configuration
BW0, BW1, BW2, BW3 7B, 7A, 5A,5B BW0, BW1 VREF VDD VDDQ VSS ZQ TMS, TDI, TCK TDO NC 7B, 5A 2H, 10H 5F, 7F, 5G, 7G, 5H, 7H, 5J, 7J, 5K, 7K 4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L 4C, 8C, 4D, 5D, 6D, 7D, 8D, 5E, 6E, 7E, 6F, 6G, 6H, 6J, 6K, 5L, 6L, 7L, 4M, 5M, 6M, 7M, 8M, 4N, 8N 11H 10R, 11R, 2R 1R 2A, 1B, 9B, 10B, 1C, 2C, 9C, 1D, 9D, 10D, 1E, 2E, 9E, 1F, 9F, 10F, 1G, 9G, 10G, 1J, 2J, 9J, 1K, 2K, 9K, 1L, 9L, 10L, 1M, 2M, 9M, 1N, 9N, 10N, 1P, 2P, 9P, 6R, 6P, 6C
NC
7A, 1B, 3B, 5B, 9B, 10B, 1C, 2C, 3C, 9C, 11C, 1D, 2D, 9D, 10D, x18 Configuration 11D, 1E, 2E, 9E, 10E, 1F, 3F, 9F, 10F, 1G, 2G, 9G, 10G, 11G, 1J, 2J, 3J, 9J, 11J, 1K, 2K, 9K, 10K, 1L, 3L, 9L, 10L, 1M, 2M, 3M, 9M, 11M, 1N, 2N, 9N, 10N, 11N, 1P, 2P, 9P, 10P, 6R, 6P, 6C
Integrated Silicon Solution, Inc.
Rev. 00A 03/31/08
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72 Mb (2M x 36 & 4M x 18) D DDR-IIP (Burst of 2) CIO Synchronous SRAMs
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Block Diagram
36 (or 18)
Data Reg Add Reg & Burst Control
36 (or 18)
Write Driver Output Select Write/Read Decode
36 (or 18) 72 (or 36)
Output Driver
Output Reg
Address A0 LD R/W BWx K K DOFF
20 (or 21)
20 (or 21)
36 (or 18) DQ (Data-Out & Data-In) CQ, CQ (Echo Clock Out)
4 (or 2)
Control Logic
2M x 36 (4M x 18) Memory Array
Clock Gen Select Output Control
SRAM Features
Read Operations
The SRAM operates continuously in a burst-of-two mode. Read cycles are started by registering R/W in active high state at the rising edge of the K clock. The K and K clocks are also used to control the timing to the outputs. The data corresponding to the first address is clocked 2.5 cycles later by the rising edge of the K clock. The data corresponding to the second burst is clocked 3 cycles later by the following rising edge of the K clock. A set of free-running echo clocks, CQ and CQ, are produced internally with timings identical to the data-outs. The echo clocks can be used as data capture clocks by the receiver device. Whenever LD is low, a new address is registered at the rising edge of the K clock. A NOP operation (LD is high) does not terminate the previous read. The output drivers disable automatically to a high state. Write Operations Write operations can also be initiated at every rising edge of the K clock whenever R/W is low. The write address is also registered at that time. When the address needs to change, LD needs to be low simultaneously to be registered by the rising edge of K. Again, the write always occurs in bursts of two. Because of its common I/O architecture, the data bus must be tri-stated at least one cycle before the new data-in is presented at the DQ bus. The write data is provided in a `late write' mode; that is, the data-in corresponding to the first address of the burst, is presented one cycle later or at the rising edge of the next K clock. The data-in corresponding to the second write burst address follows next, registered by the rising edge of K.
Sense Amps
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Integrated Silicon Solution, Inc.
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72 Mb (2M x 36 & 4M x 18) DDR-II (Burst of 2) CIO Synchronous SRAMs 72 Mb (2M x 36 & 4M x 18) DDR-IIP (Burst of 2) CIO Synchronous SRAMs D
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The data-in provided for writing is initially kept in write buffers. The information on these buffers is written into the array on the following write cycle. A read cycle to the last write address produces data from the write buffers. Similarly, a read address followed by the same write address produces the latest write data. The SRAM maintains data coherency. During a write, the byte writes independently control which byte of any of the two burst addresses is written (see X18/X36 Write Truth Tables on page 9 and Timing Reference Diagram for Truth Table on page 8). Whenever a write is disabled (R/W is high at the rising edge of K), data is not written into the memory. RQ Programmable Impedance An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to enable the SRAM to adjust its output driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the SRAM. For example, an RQ of 250 results in a driver impedance of 50. The allowable range of RQ to guarantee impedance matching is between 175 and 350, with the tolerance described in Programmable Impedance Output Driver DC Electrical Characteristics on page 13. The RQ resistor should be placed less than two inches away from the ZQ ball on the SRAM module. The capacitance of the loaded ZQ trace must be less than 3 pF. The ZQ pin can also be directly connected to VDDQ to obtain a minimum impedance setting. ZQ must never be connected to VSS. Programmable Impedance and Power-Up Requirements Periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by drifts in supply voltage and temperature. At power-up, the driver impedance is in the middle of allowable impedances values. The final impedance value is achieved within 2048 clock cycles.
Integrated Silicon Solution, Inc.
Rev. 00A 03/31/08
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72 Mb (2M x 36 & 4M x 18) DDR-IIP (Burst of 2) CIO Synchronous SRAMs
Application Example
The following figure depicts an implementation of four 4M x 18 DDR-IIP SRAMs with common I/Os.
SRAM #1
ZQ R=250 CQ/CQ
SRAM #4
ZQ R=250 CQ/CQ
Vt R
DQ0-17 SA LD R/W BW0 BW1 KK
DQ0-17 SA LD R/W BW0 BW1 KK
Data-In/Data-Out
Echo Clock Echo Clock
Address
R
Vt
LD R/W BW
Memory Controller Source CLK Source CLK
R=50 Vt=VREF
Power-Up and Power-Down Sequences
The following sequence is used for power-up: 1. The power supply inputs must be applied in the following order while keeping Doff in LOW logic state: 1) VDD 2) VDDQ 3) VREF 2. Start applying stable clock inputs (K, K, C, and C). 3. After clock signals have stabilized, change Doff to HIGH logic state. 4. Once the Doff is switched to HIGH logic state, wait an additional 1024 clock cycles to lock the DLL.
NOTES: 1. The power-down sequence must be done in reverse of the power-up sequence. 2. VDDQ can be allowed to exceed VDD by no more than 0.6V. 3. VREF can be applied concurrently with VDDQ.
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72 Mb (2M x 36 & 4M x 18) 72 Mb (2M x 36 of 2) CIO Synchronous SRAMs DDR-II (Burst & 4M x 18) DDR-IIP (Burst of 2) CIO Synchronous SRAMs D
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State Diagram
Power Up
Load NOP
Load Load Load New Address
Write
Load
Load
Read
Write
Load
DDR-IIP Read
DDR-IIP Write
Notes: 1. Read refers to read active status with R/W = high. 2. Write refers to write active status with R/W = low. 3. Load refers to read new address active status with LD = low. 4. Load is read new address inactive status with LD = high.
The Timing Reference Diagram for Truth Table on page 8 is helpful in understanding the clock and write truth tables, as it shows the cycle relationship between clocks, address, data in, data out, and controls. All read and write commands are issued at the beginning of cycle "t".
Linear Burst Sequence Table
SA0 1 0
Burst Sequence First Address Second Address
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72 D Mb (2M x 36 & 4M x 18) DDR-IIP (Burst of 2) CIO Synchronous SRAMs
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t+3
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Timing Reference Diagram for Truth Table
Cycle t Read A K Clock K Clock LD R/W BW 0,1,2,3 Address A B t+1 NOP
t+2.5 t+2 NOP
Write B
tw Write B
tw+1
Data-In/ Data-Out (DQ)
QA
QA+1
DB
CQ Clock CQ Clock
Clock Truth Table (Use the following table with the Timing Reference Diagram for Truth Table.)
Mode Stop Clock No Operation (NOP) Read A Write B Clock K Stop LH LH LH LD X H L X Controls R/W X H X L QA / DB Previous state High-Z D out at K (t + 2.5) DB (tW + 1) Data-Out/Data-In QA+1 / DB+1 Previous state High-Z D out at K (t + 3) DB (tW + 1.5)
Notes: 1. The internal burst counter is always fixed as two-bit. 2. X = don't care; H = logic "1"; L = logic "0". 3. A read operation is started when control signal R/W is active high. 4. A write operation is started when control signal R/W is active low. 5. Before entering into the stop clock, all pending read and write commands must be completed. 6. For timing definitions, refer to the AC Characteristics on page 15. Signals must have AC specifications at timings indicated in parenthesis with respect to switching clocks K and K.
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Integrated Silicon Solution, Inc.
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72 Mb (2M x 36 & 4M x 18) D DDR-IIP (Burst of 2) CIO Synchronous SRAMs
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X36 Write Truth Table Use the following table with the Timing Reference Diagram for Truth Table on
page 8.
Operation Write Byte 0 Write Byte 1 Write Byte 2 Write Byte 3 Write All Bytes Abort Write Write Byte 0 Write Byte 1 Write Byte 2 Write Byte 3 Write All Bytes Abort Write K (tw) L LH LH LH LH LH LH LH LH LH LH LH K (tw + 0.5) BW0 L H H H L H L H H H L H BW1 H L H H L H H L H H L H BW2 H H L H L H H H L H L H BW3 H H H L L H H H H L L H DB D0-8 (tw + 1) D9-17 (tw + 1) D18-26 (tw + 1) D27-35 (tw + 1) D0-35 (tw + 1) Don't care D0-8 (tw + 1.5) D9-17 (tw+1.5) D18-26 (tw+1.5) D27-35 (tw+1.5) D0-35 (tw+1.5) Don't care DB+1
Notes; 1. For all cases. R/W must be active low during the rising edge of K occurring at time tW. 2. For timing definitions, refer to the AC Characteristics on page 15. Signals must have AC specifications with respect to switching clocks K and K.
X18 Write Truth Table (Use this table with the Timing Reference Diagram for Truth Table on page 8.)
Operation Write Byte 0 on B Write Byte 1 on B Write All Bytes on B Abort Write on B Write Byte 1 on B+1 Write Byte 2 on B+1 Write All Bytes on B+1 Abort Write on B+1 K (tw) LH LH LH LH LH LH LH LH K (tw+0.5) BW0 L H L H L H L H BW1 H L L H H L L H DB D0-8 (tw + 1) D9-17 (tw + 1) D0-17 (tw + 1) Don't care D0-8 (tw + 1.5) D9-17 (tw + 1.5) D0-17 (tw + 1.5) Don't care DB+1
Notes; 1. Refer to Timing Reference Diagram for Truth Table on page 8. Cycle time starts at n and is referenced to the K clock. 2. For all cases, R/W must be active low during the rising edge of K occurring at tw. 3. For timing definitions, refer to the AC Characteristics on page 15. Signals must have AC specs with respect to switching clocks K and K.
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Rev. 00A 03/31/08
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72 Mb (2M x 36 & 4M x 18) D DDR-IIP (Burst of 2) CIO Synchronous SRAMs
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Rating -0.5 to 2.9 -0.5 to 2.9 -0.5 to VDD+0.3 -0.5 to 2.6 0 to 70 110 -55 to +125 Units V V V V C C C VDD VDDQ VIN
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Absolute Maximum Ratings
Item Power supply voltage Output power supply voltage Input voltage Data out voltage Operating temperature Junction temperature Storage temperature Symbol
VDOUT TA TJ TSTG
Note: Stresses greater than those listed in this table can cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this datasheet is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
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72 D Mb (2M x 36 & 4M x 18) DDR-IIP (Burst of 2) CIO Synchronous SRAMs
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Maximum 1.8 + 5% 1.9 VDDQ + 0.2 VREF - 0.1 0.95 VDDQ + 0.2 Units V V V V V V Notes 1 1 1, 2 1, 3 1, 5 1, 4
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Recommended DC Operating Conditions (TA = 0 to +70 C)
Parameter Supply voltage Output driver supply voltage Input high voltage Input low voltage Input reference voltage Clocks signal voltage 1. 2. 3. 4. 5. Symbol VDD VDDQ VIH VIL VREF VIN - CLK Minimum 1.8 - 5% 1.4 VREF +0.1 -0.2 0.68 -0.2 Typical
All voltages are referenced to VSS. All VDD, VDDQ, and VSS pins must be connected. VIH(Max) AC = See 0vershoot and Undershoot Timings. VIL(Min) AC = See 0vershoot and Undershoot Timings. VIN-CLK specifies the maximum allowable DC excursions of each clock (K and K). Peak-to-peak AC component superimposed on VREF may not exceed 5% of VREF.
0vershoot and Undershoot Timings
20% Min Cycle Time
VDDQ+0.6V
VIL(Min) AC Undershoot Timing
VDDQ
GND
VIH(Max) AC
Overshoot Timing
GND-0.6V 20% Min Cycle Time
PBGA Thermal Characteristics
Item Thermal resistance junction to ambient (airflow = 1m/s) Thermal resistance junction to case Thermal resistance junction to pins Symbol RJA RJC RJB Rating TBD TBD TBD Units C/W C/W C/W
Integrated Silicon Solution, Inc.
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72 Mb (2M x 36 & 4M x 18) DDR-IIP (Burst of 2) CIO Synchronous SRAMs
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Maximum 4 4 4 Units pF pF pF
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Capacitance (TA = 0 to +70 C, VDD = 1.8V -5%, +5%, f = 1MHz)
Parameter Input capacitance Data-in/Out capacitance (DQ0-DQ35) Clocks Capacitance (K and K) Symbol CIN CDQ CCLK Test Condition VIN = 0V VDIN = 0V VCLK = 0V
DC Electrical Characteristics (TA = 0 to + 70 C, VDD = 1.8V -5%, +5%)
Parameter Symbol Minimum Maximum Units Notes
x36 average power supply operating current (IOUT = 0, VIN = VIH or VIL)
IDD33 IDD40 IDD50
-- -- --
600 550 500
mA
1, 3
x18 average power supply operating current (IOUT = 0, VIN = VIH or VIL)
IDD33 IDD40 IDD50
-- -- --
600 550 500
mA
1, 3
Power supply standby current (R = VIH, W = VIH. All other inputs = VIH or VIH, IIH = 0) Input leakage current, any input (except JTAG) (VIN = VSS or VDD) Output leakage current (VOUT = VSS or VDDQ, Q in High-Z) Output "high" level voltage (IOH = -6mA) Output "low" level voltage (IOL = +6mA) JTAG leakage current (VIN = VSS or VDD)
ISBSS ILI ILO VOH VOL ILIJTAG
-- -2 -2 VDDQ -.4 VSS -100
200 +2 +2 VDDQ VSS+.4 +100
mA uA uA V V uA
1
2, 4 2, 4 5
1. IOUT = chip output current. 2. Minimum impedance output driver. 3. The numeric suffix indicates the part operating at speed, as indicated in AC Characteristics on page 15. 2 4. JEDEC Standard JESD8-6 Class 1 compatible. 5. For JTAG inputs only. 6. Currents are estimates only and need to be verified.
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Integrated Silicon Solution, Inc.
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D Mb (2M x 36 & 4M x 18) 72 DDR-IIP (Burst of 2) CIO Synchronous SRAMs
Typical AC Input Characteristics
Item AC input logic high AC input logic low Clock input logic high (K, K) Clock input logic low (K, K) 1. 2. 3. 4. Symbol VIH (ac) VIL (ac) VIH-CLK (ac) VIL-CLK (ac) VREF + 0.2 VREF - 0.2 Minimum VREF + 0.2 VREF - 0.2 Maximum
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Notes 1, 2, 3, 4 1, 2, 3, 4 1, 2, 3 1, 2, 3
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The peak-to-peak AC component superimposed on VREF may not exceed 5% of the DC component of VREF. Performance is a function of VIH and VIL levels to clock inputs. See the AC Input Definition diagram. See the AC Input Definition diagram. The signals should swing monotonically with no steps rail-to-rail with input signals never ringing back past VIH (AC) and VIL (AC) during the input setup and input hold window. VIH (AC) and VIL (AC) are used for timing purposes only.
AC Input Definition
K
VREF
K VRAIL VIH (AC) VREF
Setup Time
Hold Time
VIL (AC)
V-RAIL
Programmable Impedance Output Driver DC Electrical Characteristics
(TA = 0 to +70 C, VDD = 1.8V -5%, +5%, VDDQ = 1.5, 1.8V)
Parameter Output "high" level voltage Output "low" level voltage
VDDQ 1. IOH = ------------------ 2
Symbol VOH VOL
Minimum VDDQ / 2 VSS
Maximum VDDQ VDDQ / 2
Units V V
Notes 1, 3 2, 3
RQ ------- 5 15% @ VOH = VDDQ / 2 For: 175 RQ 350.
VDDQ RQ 2. IOL = ------------------ -------- 15% @ VOL = VDDQ / 2 For: 175 RQ 350. 2 5
3. Parameter tested with RQ = 250 and VDDQ = 1.5V.
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D 72 Mb (2M x 36 & 4M x 18) DDR-IIP (Burst of 2) CIO Synchronous SRAMs
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Conditions 1.5, 1.8 VREF+0.5 VREF-0.5 0.75, 0.9 0.35 0.35 VREF VREF Units V V V V ns ns V V 1, 2 Notes
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AC Test Conditions (TA = 0 to +70 C, VDD = 1.8V -5%, +5%, VDDQ = 1.5, 1.8V)
Parameter Output driver supply voltage Input high level Input Low Level Input reference voltage Input rise time Input fall time Output timing reference level Clocks reference level Output load conditions 1. See AC Test Loading. 2. Parameter tested with RQ = 250 and VDDQ = 1.5V. Symbol VDDQ VIH VIL VREF TR TF
AC Test Loading
50 Q 50 0.75, 0.9V Test Comparator
5pF 0.75, 0.9V
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Integrated Silicon Solution, Inc.
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72 Mb (2M x 36 & 4M x 18) DDR-IIP (Burst of 2) CIO Synchronous SRAMs
AC CHARACTERISTICS (Vdd = 1.8V + 0.1V, TA = 0 C to 70 C)
DDR IIP ISSI Parameter Description min tKHKH tKHKL tKLKH tKHKH Setup Times tAVKH tIVKH tIVKH tDVKH Hold Times tKHAX tKHIX tKHIX tKHDX Output Times tCHQV tCHQX tCHCQV tCHCQX tCQHQV tCQHQX tCHQZ tCHQX1 DLL Timing tKC Var tKC lock tDoffLowToReset Notes:
1. See AC Test Loading on page 14. 2. During normal operation, VIH, VIL, TRISE, and TFALL of inputs must be within 20% of VIH, VIL, TRISE, and TFALL of clock.
400 max min
375 max min
333 max min
300 max
unit
notes
K Clock Cycle Time Input Clock (K/K) HIGH Input Clock (K/K) LOW K Clock Rise to K Clock Rise (rising edge to rising edge) Address Setup to K Clock Rise Control Setup to K Clock Rise (R, W) Double Data Rate Control Setup to Clock (K, K) Rise (BWS 0, BWS 1, BWS 2, BWS 3) Data Input Setup to Clock (K/K) Rise Address Hold after K Clock Rise Control Hold after K Clock Rise Double Data Rate Control Hold after Clock (K/K) Rise (BWS 0, BWS 1, BWS 2, BWS 3) Data Input Hold after Clock (K/K) Rise K/K Clock Rise to Data Valid Data Output Hold after Output K/K Clock Rise (Active to Active) K/K Clock Rise to Echo Clock Valid Echo Clock Hold after K/K Clock Rise Echo Clock High to Data Valid Echo Clock High to Data Invalid Clock (K/K) Rise to High-Z (Active to High-Z) Clock (K/K) Rise to Low-Z Clock Phase Jitter DLL Lock Time (K) Doff Low period to DLL Reset
2.50 7.50 2.66 7.50 0.40 0.40 1.06 0.40 0.40 1.13
3.00 7.50 0.40 0.40 1.28
3.30 7.50 0.40 0.40 1.40
ns tKHKH tKHKH ns
0.40 0.40 0.28 0.28 0.40 0.40 0.28 0.28 0.45 -0.45 0.45 -0.45 0.20 -0.20 0.45 -0.45 0.20 2048 5
0.40 0.40 0.28 0.28 0.40 0.40 0.28 0.28 0.45 -0.45 0.45 -0.45 0.20 -0.20 0.45 -0.45 0.20 2048 5
0.40 0.40 0.28 0.28 0.40 0.40 0.28 0.28 0.45 -0.45 0.45 -0.45 0.20 -0.20 0.45 -0.45 0.20 2048 5
0.40 0.40 0.28 0.28 0.40 0.40 0.28 0.28 0.45 -0.45 0.45 -0.45 0.20 -0.20 0.45 -0.45 0.20
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns cycles ns
2 2 2 2
1 1
1 1 1 1
Integrated Silicon Solution, Inc.
Rev. 00A 03/31/08
15
72 Mb (2M x 36 & 4M x 18) DDR-IIP (Burst of 2) CIO Synchronous SRAMs
Read, Write, and NOP Timing Diagram
NOP 1 K
tKHKL
Read 2
(burst of 2) (burst of 2) (burst of 2)
Read
Read
NOP 5
NOP 6
(Note 3)
Write 7
(burst of 2) (burst of 2) (burst of 2)
Write
Read 9
Read 10
(burst of 2)
NOP 11
NOP 12
3
4
4.5
8
tKHKH tKHKL K tIVKH tKHIX LD R/W SA
tAVKH tKHAX
tKHKH tKLKH
A0
A1
tCHQV tCHQX1
Q01
A2
A3
A4 tDVKH tKHDX
A5
tCHQX
Q02 Q11
tCHQZ
Q12
tCHQV
Q41 Q42
DQ
D21 D22 D31 D32
tCHCQV tCHCQX
CQ
tCHCQV tCHCQX
CQ
Don't Care
Undefined
16
Integrated Silicon Solution, Inc.
Rev. 00A 03/31/08
72 Mb (2M x 36 & 4M x 18) DDR-IIP (Burst of 2) CIO Synchronous SRAMs D
I
IEEE 1149.1 TAP and Boundary Scan The SRAM provides a limited set of JTAG functions to test the interconnection between SRAM I/Os and printed circuit board traces or other components. There is no multiplexer in the path from I/O pins to the RAM core. In conformance with IEEE Standard 1149.1, the SRAM contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. The TAP controller has a standard 16-state machine that resets internally on power-up. Therefore, a TRST signal is not required. Signal List * * * * TCK: test clock TMS: test mode select TDI: test data-in TDO: test data-out
3
JTAG DC Operating Characteristics (TA = 0 to +70 C)
Operates with JEDEC Standard 8-5 (1.8V) logic signal levels
Parameter JTAG input high voltage JTAG input low voltage JTAG output high level JTAG output low level 1. 2. 3. All JTAG inputs and outputs are LVTTL-compatible. IOH1 -2mA IOL1 +2mA. Symbol VIH1 VIL1 VOH1 VOL1 Minimum 1.3 -0.3 VDD-0.4 VSS Typical -- -- -- -- Maximum VDD+0.3 0.5 VDD 0.4 Units V V V V Notes 1 1 1, 2 1, 3
JTAG AC Test Conditions (TA = 0 to +70 C, VDD = 1.8V -5%, +5%)
Parameter Input pulse high level Input pulse low level Input rise time Input fall time Input and output timing reference level Symbol VIH1 VIL1 TR1 TF1 Conditions 1.3 0.5 1.0 1.0 0.9 Units V V ns ns V
Integrated Silicon Solution, Inc.
Rev. 00A 03/31/08
17
72 Mb (2M x 36 & 4M x 18) D DDR-IIP (Burst of 2) CIO Synchronous SRAMs
I
Maximum -- -- -- -- -- -- -- 7 Units ns ns ns ns ns ns ns ns 1 Notes 20 7 7 4 4 4 4 --
3
JTAG AC Characteristics (TA = 0 to +70 C, VDD = 1.8V -5%, +5%)
Parameter TCK cycle time TCK high pulse width TCk low pulse width TMS setup TMS hold TDI setup TDI hold TCK low to valid data 1. See AC Test Loading on page 14. Symbol tTHTH tTHTL tTLTH tMVTH tTHMX tDVTH tTHDX tTLOV Minimum
JTAG Timing Diagram
tTHTL tTLTH tTHTH
TCK
tTHMX
TMS tMVTH
tTHDX
TDI
tDVTH
TDO
tTLOV
18
Integrated Silicon Solution, Inc.
Rev. 00A 03/31/08
72 Mb (2M x 36 & 4M x 18) D DDR-IIP (Burst of 2) CIO Synchronous SRAMs
I
Bit Size x18 or x36 3 1 32 109
3
Scan Register Definition
Register Name Instruction Bypass ID Boundary Scan
ID Register Definition
Field Bit Number and Description Part 4M x 18 2M x 36 Revision Number (31:29) 000 000 Part Configuration (28:12) 00def0wx0t0q0b0s0 00def0wx0t0q0b0s0 JEDEC Code (11:1) 000 101 001 00 000 101 001 00 Start Bit (0) 1 1
Part Configuration Definition: def = 011 for 72Mb wx = 11 for x36, 10 for x18 t = 1 for DLL, 0 for non-DLL q = 1 for QUADB2, 0 for DDR-II, DDR-IIP b = 1 for burst of 4, 0 for burst of 2 s = 1 for separate I/0, 0 for common I/O
Integrated Silicon Solution, Inc.
Rev. 00A 03/31/08
19
72 Mb (2M x 36 & 4M x 18) D DDR-IIP (Burst of 2) CIO Synchronous SRAMs
Instruction Set
Code 000 001 010 011 100 101 110 111 Instruction EXTEST IDCODE SAMPLE-Z PRIVATE SAMPLE PRIVATE PRIVATE BYPASS TDO Output Boundary Scan Register 32-bit Identification Register Boundary Scan Register Do not use Boundary Scan Register Do not use Do not use Bypass Register 1, 2 5 4 5 5 3 Notes 2,6
I
3
1. Places Qs in high-Z in order to sample all input data, regardless of other SRAM inputs. 2. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data. 3. BYPASS register is initiated to VSS when BYPASS instruction is invoked. The BYPASS register also holds the last serially loaded TDI when exiting the shift-DR state. 4. SAMPLE instruction does not place DQs in high-Z. 5. This instruction is reserved. Invoking this instruction will cause improper SRAM functionality. 6. This EXTEST is not IEEE 1149.1-compliant. By default, it places Q in high-Z. If the internal register on the scan chain is set high, Q will be updated with information loaded via a previous SAMPLE instruction. The actual transfer occurs during the update IR state after EXTEST is loaded. The value of the internal register can be changed during SAMPLE and EXTEST only.
List of IEEE 1149.1 Standard Violations * * * * * 7.2.1.b, e 7.7.1.a-f 10.1.1.b, e 10.7.1.a-d 6.1.1.d
JTAG Block Diagram
TDI
Bypass Register (1 bit) Identification Register (32 bits) Instruction Register (3 bits) TDO
Control Signals
TMS TCK
TAP Controller
20
Integrated Silicon Solution, Inc.
Rev. 00A 03/31/08
72 Mb (2M x 36 & 4M x 18) D DDR-IIP (Burst of 2) CIO Synchronous SRAMs
I
3
TAP Controller State Machine
1
Test Logic Reset 0 0 Run Test Idle 1 Select DR 0 1 1 Capture DR 0 0 Shift DR 1 1 1 Exit1 DR 0 0 0 0 Pause IR 1 0 Exit1 IR 0 Shift IR 1 1 Select IR 0 Capture IR 0 1
Pause DR 1
Exit2 DR 0 1 1 Update DR 0 1
Exit2 IR 1 Update IR 0
Integrated Silicon Solution, Inc.
Rev. 00A 03/31/08
21
72 Mb (2M x 36 & 4M x 18) D DDR-IIP (Burst of 2) CIO Synchronous SRAMs D
I
3
Boundary Scan Exit Order The same length is used for x18 and x36 I/O configuration.
Order 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Pin ID 6R 6P 6N 7P 7N 7R 8R 8P 9R 11P 10P 10N 9P 10M 11N 9M 9N 11L 11M 9L 10L 11K 10K 9J 9K 10J 11J 11H 10G 9G 11F 11G 9F 10F 11E 10E Order 37 37 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Pin ID 10D 9E 10C 11D 9C 9D 11B 11C 9B 10B 11A 10A 9A 8B 7C 6C 8A 7A 7B 6B 6A 5B 5A 4A 5C 4B 3A 2A 1A 2B 3B 1C 1B 3D 3C 1D Order 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 Notes: 1) NC pins as defined on FBGA pinouts on page 2 are read as "don't cares". 2) State of Internal pin (#109) is loaded via JTAG Pin ID 2C 3E 2D 2E 1E 2F 3F 1G 1F 3G 2G 1H 1J 2J 3K 3J 2K 1K 2L 3L 1M 1L 3N 3M 1N 2M 3P 2N 2P 1P 3R 4R 4P 5P 5N 5R Internal
22
Integrated Silicon Solution, Inc.
Rev. 00A 03/31/08
72 Mb (2M x 36 & 4M x 18) DDR-IIP (Burst of 2) CIO Synchronous SRAMs
11 x 15 FBGA Dimensions
Integrated Silicon Solution, Inc.
Rev. 00A 03/31/08
23
72 Mb (2M x 36 & 4M x 18) DDR-IIP (Burst of 2) CIO Synchronous SRAMs
ORDeRInG InfORMAtIOn Commercial Range: 0C to +70C
Speed 400 MHz Order Part no. IS61DDPB22M36-400M3 IS61DDPB22M36-400M3L IS61DDPB24M18-400M3 IS61DDPB24M18-400M3L IS61DDPB22M36-375M3 IS61DDPB22M36-375M3L IS61DDPB24M18-375M3 IS61DDPB24M18-375M3L Organization 2Mx36 2Mx36 4Mx18 4Mx18 2Mx36 2Mx36 4Mx18 4Mx18 Package 165 BGA 165 BGA, Lead-free 165 BGA 165 BGA, Lead-free 165 BGA 165 BGA, Lead-free 165 BGA 165 BGA, Lead-free
375 MHz
24
Integrated Silicon Solution, Inc.
Rev. 00A 03/31/08

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